Mealy Moore finite state machine RTL to Gate level conversion and comparison

This article is about the comparison of rtl from different tools for earlier design level to pulse converter. Please refer the article level-to-pulse-converter for more details. It is continuous part of that article only.

level to pulse converter rtl design

for the experiment we took the same code from the earlier L-to-P converter circuit code for reference here  also we place for you.

code is given below for moore fsm

library IEEE;
use IEEE.std_logic_1164.all;
entity moore_LTP_fsm1 is
port (
clk: in STD_LOGIC;
L: in STD_LOGIC;
rst: in STD_LOGIC;
P: out STD_LOGIC);
end moore_LTP_fsm1;
architecture moore_LTP_fsm1_arch of moore_LTP_fsm1 is
-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (
S1, S2, S3
);
-- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
signal Sreg0, NextState_Sreg0: Sreg0_type;
-- Declarations of pre-registered internal signals
signal int_P, next_P: STD_LOGIC;
begin
-- concurrent signals assignments
-- Diagram ACTION
----------------------------------------------------------------------
-- Machine: Sreg0
----------------------------------------------------------------------
------------------------------------
-- Next State Logic (combinatorial)
------------------------------------
Sreg0_NextState: process (int_P, L, Sreg0)
begin
NextState_Sreg0 <= Sreg0;
-- Set default values for outputs and signals
next_P <= int_P;
case Sreg0 is
when S1 =>
next_P <= '0';
if L='1' then
NextState_Sreg0 <= S2;
elsif L='0' then
NextState_Sreg0 <= S1;
end if;
when S2 =>
next_P <= '1';
if L='0' then
NextState_Sreg0 <= S1;
elsif L='1' then
NextState_Sreg0 <= S3;
end if;
when S3 =>
next_P <= '0';
if L='0' then
NextState_Sreg0 <= S1;
elsif L='1' then
NextState_Sreg0 <= S3;
end if;
--vhdl_cover_off
when others =>
null;
--vhdl_cover_on
end case;
end process;
------------------------------------
-- Current State Logic (sequential)
------------------------------------
Sreg0_CurrentState: process (clk)
begin
if clk'event and clk = '1' then
if rst='1' then
Sreg0 <= S1;
else
Sreg0 <= NextState_Sreg0;
end if;
end if;
end process;
------------------------------------
-- Registered Outputs Logic
------------------------------------
Sreg0_RegOutput: process (clk)
begin
if clk'event and clk = '1' then
if rst='1' then
int_P <= '0';
else
int_P <= next_P;
end if;
end if;
end process;
-- Copy temporary signals to target output ports
P <= int_P;
end moore_LTP_fsm1_arch;

code is given below for mealy fsm


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_signed.all;
entity mealy_LTP_fsm1 is
port (
clk: in STD_LOGIC;
L: in STD_LOGIC;
rst: in STD_LOGIC;
P: out STD_LOGIC);
end mealy_LTP_fsm1;
architecture mealy_LTP_fsm1_arch of mealy_LTP_fsm1 is
-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (
S3, S4
);
-- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding
signal Sreg0: Sreg0_type;
begin
-- concurrent signals assignments
-- Diagram ACTION
----------------------------------------------------------------------
-- Machine: Sreg0
----------------------------------------------------------------------
Sreg0_machine: process (clk)
begin
if clk'event and clk = '1' then
if rst='1' then
Sreg0 <= S3;
-- Set default values for outputs, signals and variables
-- ...
P <= '0'; else -- Set default values for outputs, signals and variables -- ... case Sreg0 is when S3 =>
P <= '0';
if L='1' then
Sreg0 <= S4;
P <= '1';
elsif L='0' then
Sreg0 <= S3; end if; when S4 =>
P <= '0';
if L='1' then
Sreg0 <= S4;
elsif L='0' then
Sreg0 <= S3;
P <= '0'; end if; --vhdl_cover_off when others =>
null;
--vhdl_cover_on
end case;
end if;
end if;
end process;
end mealy_LTP_fsm1_arch;

Here i took the fsm code of moore m/c and mealy m/c and try to get the rtl from dc synopsys and rc complier from cadence, for check how these tool maps the code into better rtl. The snaps from dc and rc compiler for moore and mealy sequentially.

It is dc generated rtl for moore fsm, looks lots of cell are there, from cell report it is around 15 cells, if you remeber the manual map design for the same tooks only 2 flops and 2 gates for ref i shown below.

its critical path, from dc tool itself.

now from cadence tool rtl comes as similar as this, take a look

but it took less number of cells, only 14 , here looks cadence mapping in better way.

Now same for mealy, what i got is as below.

it shows the critical path, from rtl schematic number of cells are 7

from rc compiler , total cells are 5, here also cadence is little better rtl mapper,

one might wondering, tcl script or technology i may set wrong which result in diff cell number, but i used same technology for all rtl transfer and same hdl code, with all proper setting of optimization. hope you get what i mean. Please do comment, like. we will bring similar articles for you.