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EDA tool tcl script

Byadmin

Mar 8, 2023

The tcl script helps to control the EDA tools and automate the flow control. Now days every eda tools handles via tcl script even analoge design tools also.

1] Design Vision Compiler [DC ]

 

script 1

#/**************************************************/
#/* Compile Script for Synopsys */
#/* OSU FreePDK 45nm */
#/**************************************************/
file mkdir ../results/dc45
#/* All verilog files, separated by spaces */

#set fileFormat verilog ;# verilog or VHDL
#set fileFormat VHDL ;# verilog or VHDL

set my_hdl_files [list ../code/ ] # keep source files under code folder and specify each files separate with space 

#/* Top-level Module */
set my_toplevel xxxxxx

#/* The name of the clock pin. If no clock-pin */
#/* exists, pick anything */
set my_clock_pin clk
#create_clock -period 40 -waveform {0 20} -name clk

#/* Target frequency in MHz for optimization */
set my_clk_freq_MHz 50

#/* Delay of input signals (Clock-to-Q, Package etc.) */
set my_input_delay_ns 0.1

#/* Reserved time for output signals (Holdtime etc.) */
set my_output_delay_ns 0.1

#/**************************************************/
#/* No modifications needed below */
#/**************************************************/
set OSU_FREEPDK >> path to /osu_freepdk/lib/files
set search_path [concat $search_path $OSU_FREEPDK]
set alib_library_analysis_path $OSU_FREEPDK

set link_library [set target_library [concat [list gscl45nm.db] [list dw_foundation.sldb]]]
set target_library “gscl45nm.db”
define_design_lib WORK -path ../WORK
set verilogout_show_unconnected_pins “true”
set_ultra_optimization true
set_ultra_optimization -force

analyze -f vhdl $my_hdl_files
#analyze -f verilog $my_hdl_files

elaborate $my_toplevel

current_design $my_toplevel

link
uniquify

set my_period [expr 1000 / $my_clk_freq_MHz]

set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock != [list] } {
set clk_name $my_clock_pin
create_clock -period $my_period $clk_name
} else {
set clk_name vclk
create_clock -period $my_period -name $clk_name
}

set_driving_cell -lib_cell INVX1 [all_inputs]
set_input_delay $my_input_delay_ns -clock $clk_name [remove_from_collection [all_inputs] $my_clock_pin]
set_output_delay $my_output_delay_ns -clock $clk_name [all_outputs]

compile -ungroup_all -map_effort medium

compile -incremental_mapping -map_effort medium

check_design
report_constraint -all_violators

set filename [format “%s%s” $my_toplevel “s45.v”]
write -f verilog -output ../results/dc45/$filename
write -f verilog -output ../enc/$filename

set filename [format “%s%s” $my_toplevel “s45.sdc”]
write_sdc ../results/dc45/$filename
write_sdc ../enc/$filename

redirect ../results/dc45/timing45.rep { report_timing }
redirect ../results/dc45/cell45.rep { report_cell }
redirect ../results/dc45/power45.rep { report_power }

redirect ../results/dc45/report_time45.txt {report_timing -path full -delay max -max_paths 1 -nworst 1}
redirect ../results/dc45/report_area45.txt {report_area}
redirect ../results/dc45/report_power45.txt {report_power}
exec cat ../results/dc45/report_area45.txt ../results/dc45/report_power45.txt ../results/dc45/report_time45.txt > ../results/dc45/report_all45.txt

script 2

#/**************************************************/
#/* Compile Script for Synopsys */
#/**************************************************/
file mkdir ../results/dc90
#/* All verilog files, separated by spaces */
#set fileFormat verilog ;# verilog or VHDL
#set fileFormat VHDL ;# verilog or VHDL

set my_hdl_files [list ../code/ ] # keep source files under code folder and specify each files separate with space 

#/* Top-level Module */
set my_toplevel xxxxxx

#/* The name of the clock pin. If no clock-pin */
#/* exists, pick anything */
set my_clock_pin clk
#create_clock -period 40 -waveform {0 20} -name clk

#/* Target frequency in MHz for optimization */
set my_clk_freq_MHz 50

#/* Delay of input signals (Clock-to-Q, Package etc.) */
set my_input_delay_ns 0.1

#/* Reserved time for output signals (Holdtime etc.) */
set my_output_delay_ns 0.1

#/**************************************************/
#/* No modifications needed below */
#/**************************************************/

set saed90 >> path to /90nm/models
set search_path ${saed90}
set link_library ${saed90}/saed90nm_typ_ht.db
set target_library ${saed90}/saed90nm_typ_ht.db
set symbol_library ${saed90}/saed90nm.sdb
set define_design_lib WORK -path ./WORK

alias h history
alias rc “report_constraint -all_violators”

set verilogout_show_unconnected_pins “true”
set_ultra_optimization true
set_ultra_optimization -force

analyze -f vhdl $my_hdl_files
#analyze -f verilog $my_hdl_files

elaborate $my_toplevel

current_design $my_toplevel

link
uniquify

set my_period [expr 1000 / $my_clk_freq_MHz]

set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock != [list] } {
set clk_name $my_clock_pin
create_clock -period $my_period $clk_name
} else {
set clk_name vclk
create_clock -period $my_period -name $clk_name
}

set_driving_cell -lib_cell INVX1 [all_inputs]
set_input_delay $my_input_delay_ns -clock $clk_name [remove_from_collection [all_inputs] $my_clock_pin]
set_output_delay $my_output_delay_ns -clock $clk_name [all_outputs]

set_fix_hold clk

set_wire_load_mode “segmented”
set_max_area 0

compile -ungroup_all -map_effort medium

compile -incremental_mapping -map_effort medium

check_design
report_constraint -all_violators

set filename [format “%s%s” $my_toplevel “90.v”]
write -f verilog -output ../results/dc90/$filename
write -f verilog -output ../icc/$filename

set filename [format “%s%s” $my_toplevel “90.sdc”]
write_sdc ../results/dc90/$filename
write_sdc ../icc/$filename

redirect ../results/dc90/timing90.rep { report_timing }
redirect ../results/dc90/cell90.rep { report_cell }
redirect ../results/dc90/power90.rep { report_power }

redirect ../results/dc90/report_time90.txt {report_timing -path full -delay max -max_paths 1 -nworst 1}
redirect ../results/dc90/report_area90.txt {report_area}
redirect ../results/dc90/report_power90.txt {report_power}
exec cat ../results/dc90/report_area90.txt ../results/dc90/report_power90.txt ../results/dc90/report_time90.txt > ../results/dc90/report_all90.txt

Here two script is given you can refer any one and edit the path, top module name according to your requirement, it is template of script.

 2] rc-compiler

##this tells the compiler where to look for the libraries

set_attribute lib_search_path  >>path>>/libfortech/osu_freepdk/lib/files

## This defines the libraries to use

set_attribute library {gscl45nm.lib}

##This must point to your VHDL/verilog file
## CHANGE THIS LINE to your VHDL/verilog file name,

file mkdir ../results/rtl

read_hdl -vhdl [list ../code/xxxxx.vhd]

set my_toplevel xxxxx

## This buils the general block
elaborate

##this allows you to define a clock and the maximum allowable delays
#set clock [define_clock -period 300 -name clk]
#external delay -input 300 -edge rise clk
#external delay -output 2000 -edge rise p1

ungroup -all -flatten
##This synthesizes your code
#synthesize -to_mapped
synthesize -effort low -to_mapped

## This writes all your files
## change the tst to the name of your top level verilog

set filename [format “%s%s” $my_toplevel “rc.vh”]
##write_sdc ../results/dc45/$filename

write -mapped > ../results/rtl/$filename
write -mapped > /Cadence/CMOSedu/all_vh_files/$filename
write -mapped > ../enc/$filename

write_script > ../results/rtl/script

set filename [format “%s%s” $my_toplevel “rc.sdc”]

write_sdc > ../results/rtl/$filename
write_sdc > ../enc/$filename

set filename [format “%s%s” $my_toplevel “_ref_power_rc45.txt”]
build_rtl_power_models -clean_up_netlist
report power -rtl_cross_reference > ../results/rtl/$filename
set filename [format “%s%s” $my_toplevel “_hierarchy_power_rc45.txt”]
report power -rtl -flat > ../results/rtl/$filename
set filename [format “%s%s” $my_toplevel “_area_rc45.txt”]
report area -rtl -flat > ../results/rtl/$filename
set filename [format “%s%s” $my_toplevel “_timing_rc45.txt”]
report timing > ../results/rtl/$filename

3] IC compiler [icc]

set saed90 /path>>/90nm/models
set search_path ${saed90}
set link_library ${saed90}/saed90nm_typ_ht.db
set target_library ${saed90}/saed90nm_typ_ht.db
set symbol_library ${saed90}/saed90nm.sdb
set define_design_lib WORK -path ./WORK
alias h history
alias rc “report_constraint -all_violators”

file mkdir ../results/icc

set my_toplevel xxxxx

# ——– defination.tcl

create_mw_lib -technology /path>> /90nm/techfiles/saed90nm_icc_1p9m.tf \
-mw_reference_library {/path >> /90nm/saed90nm_fr } \
-hier_separator {/} \
-bus_naming_style {[%d]} \
-open ../results/icc/COUNT

set_tlu_plus_files -max_tluplus /path>> /90nm/tluplus/saed90nm_1p9m_1t_Cmax.tluplus \
-min_tluplus /path>> /90nm/tluplus/saed90nm_1p9m_1t_Cmin.tluplus \
-tech2itf_map /path>> /90nm/tluplus/tech2itf.map

set filename [format “%s%s” $my_toplevel “90.v”]
read_verilog -cell $my_toplevel ../icc/$filename

# -allow_undefined_module
#import_designs -format verilog \
# -top $my_toplevel \
# -cel $my_toplevel {../results/enc90/fsmdemo190.v}

set filename [format “%s%s” $my_toplevel “90.sdc”]
source ../icc/$filename

# ——– degsineall.tcl

# ## FLOORPLAN
# ################################################################
initialize_floorplan -core_utilization 0.33 -start_first_row -flip_first_row -left_io2core 1 -bottom_io2core 1 -right_io2core 1 -top_io2core 1

current_design $my_toplevel

set power “VDD”
set ground “VSS”
set powerPort “VDD”
set groundPort “VSS”
set mw_logic0_net “VSS”
set mw_logic1_net “VDD”

# DEFINING POWER/GROUND NETS AND PINS
derive_pg_connection -power_net VDD \
-ground_net VSS \
-power_pin VDD \
-ground_pin VSS

##//CREATING POWER RECTANGULAR RING

create_rectangular_rings -nets {VDD VSS} -left_offset 0.2 -left_segment_layer M4 -right_offset 0.2 -right_segment_layer M4 -bottom_offset 0.2 -bottom_segment_layer M3 -extend_bh -top_offset 0.2 -top_segment_layer M3

create_power_straps -direction horizontal -nets {VDD} -layer M4 -configure groups_and_step -num_groups 28 -step 3
create_power_straps -direction horizontal -start_at 1.5 -nets {VSS} -layer M4 -configure groups_and_step -num_groups 28 -step 3
create_power_straps -direction vertical -nets {VDD} -layer M3 -configure groups_and_step -num_groups 28 -step 3
create_power_straps -direction vertical -start_at 1.5 -nets {VSS} -layer M3 -configure groups_and_step -num_groups 28 -step 3

puts “start_place”

## This should be changed back once we figure out how to deal with read_def!!!!
## place_opt -effort high -optimize_dft -congestion
place_opt -effort high -continue_on_missing_scandef -congestion

legalize_placement -effort high -incremental

set_fix_multiple_port_nets -all -buffer_constants

## This should be changed back once we figure out how to deal with read_def!!!!
## place_opt -effort high -optimize_dft -congestion
place_opt -effort high -continue_on_missing_scandef -congestion

legalize_placement -effort high -incremental

preroute_standard_cells -nets VSS -connect horizontal
preroute_standard_cells -nets VDD -connect horizontal

verify_pg_nets -pad_pin_connection all
save_mw_cel

puts “finish_place”

puts “start_cts”

check_legality

set_clock_tree_options -clock_trees clk \
-insert_boundary_cell true \
-ocv_clustering true \
-buffer_relocation true \
-buffer_sizing true \
-gate_relocation true \
-gate_sizing true \
-delay_insertion true

set cts_use_debug_mode true
set cts_do_characterization true

puts “stdcell_filler”

clock_opt -fix_hold_all_clocks

# DEFINING POWER/GROUND NETS AND PINS
derive_pg_connection -power_net VDD \
-ground_net VSS \
-power_pin VDD \
-ground_pin VSS

preroute_standard_cells -nets VSS -connect horizontal
preroute_standard_cells -nets VDD -connect horizontal

verify_pg_nets
verify_pg_nets -pad_pin_connection all

save_mw_cel

puts “finish_cts”

puts “start_route”

check_routeability

set_delay_calculation -arnoldi

set_net_routing_layer_constraints \
-max_layer_name M5 -min_layer_name M1 {*}

set_si_options -route_xtalk_prevention true\
-delta_delay true \
-min_delta_delay true \
-static_noise true\
-max_transition_mode normal_slew \
-timing_window true

set_route_options -groute_timing_driven true \
-groute_incremental true \
-track_assign_timing_driven true \
-same_net_notch check_and_fix

route_opt -effort high \
-stage global \
-incremental

save_mw_cel

route_opt -effort high \
-stage track \
-xtalk_reduction \
-optimize_wire_via \
-incremental

save_mw_cel

verify_route

insert_redundant_vias -auto_mode insert

insert_stdcell_filler -cell_without_metal SHFILL1 \
-connect_to_power VDD -connect_to_ground VSS

insert_stdcell_filler -cell_without_metal SHFILL2 \
-connect_to_power VDD -connect_to_ground VSS

insert_well_filler -layer NWELL \
-higher_edge max -lower_edge min

preroute_standard_cells -nets VDD -connect horizontal
preroute_standard_cells -nets VSS -connect horizontal

verify_pg_nets
verify_pg_nets -pad_pin_connection all

route_search_repair -loop 500 -rerun_drc

save_mw_cel

puts “finish_route”

close_mw_cel
close_mw_lib
set_mw_lib_reference -mw_reference_library {/path>> /90nm/saed90nm_fr} ../results/icc/COUNT/
open_mw_lib ../results/icc/COUNT
set ::auto_restore_mw_cel_lib_setup false
open_mw_cel $my_toplevel

set_write_stream_options -map_layer /path>> /90nm/saed90nm.gdsout.map \
-output_filling fill \
-child_depth 20 \
-output_outdated_fill \
-output_pin {text geometry}
write_stream -lib ../results/icc/COUNT\
-format gds\
-cells $my_toplevel\
../results/icc/$my_toplevel.gds

extract_rc

write_parasitics -output ../results/icc/$my_toplevel.spef
write_verilog -pg -no_physical_only_cells ../results/icc/$my_toplevel.v1
write_verilog -no_physical_only_cells ../results/icc/$my_toplevel.v

4] Encounter 

encounter_rc.conf

##########################################
# FirstEncounter Input configuration file #
################################################
# Specify the name of your toplevel module
set my_toplevel xxxx

################################################
# No changes required below
################################################

global env
set OSU_FREEPDK /path>> /osu_freepdk/
#set OSU_FREEPDK $env(OSU_FREEPDK)

global rda_Input

set filename [format “%s%s” $my_toplevel “rc.vh”]
set rda_Input(ui_netlist) ../enc/$filename
set filename [format “%s%s” $my_toplevel “rc.sdc”]
set rda_Input(ui_timingcon_file) ../enc/$filename
set rda_Input(ui_topcell) $my_toplevel

set rda_Input(ui_netlisttype) {Verilog}
set rda_Input(ui_ilmlist) {}
set rda_Input(ui_settop) {1}
set rda_Input(ui_celllib) {}
set rda_Input(ui_iolib) {}
set rda_Input(ui_areaiolib) {}
set rda_Input(ui_blklib) {}
set rda_Input(ui_kboxlib) “”
set rda_Input(ui_timelib) “$OSU_FREEPDK/lib/files/gscl45nm.tlf”
set rda_Input(ui_smodDef) {}
set rda_Input(ui_smodData) {}
set rda_Input(ui_dpath) {}
set rda_Input(ui_tech_file) {}
set rda_Input(ui_io_file) “”
set rda_Input(ui_buf_footprint) {buf}
set rda_Input(ui_delay_footprint) {buf}
set rda_Input(ui_inv_footprint) {inv}
set rda_Input(ui_leffile) “$OSU_FREEPDK/lib/files/gscl45nm.lef”
set rda_Input(ui_core_cntl) {aspect}
set rda_Input(ui_aspect_ratio) {1.0}
set rda_Input(ui_core_util) {0.7}
set rda_Input(ui_core_height) {}
set rda_Input(ui_core_width) {}
set rda_Input(ui_core_to_left) {}
set rda_Input(ui_core_to_right) {}
set rda_Input(ui_core_to_top) {}
set rda_Input(ui_core_to_bottom) {}
set rda_Input(ui_max_io_height) {0}
set rda_Input(ui_row_height) {}
set rda_Input(ui_isHorTrackHalfPitch) {0}
set rda_Input(ui_isVerTrackHalfPitch) {1}
set rda_Input(ui_ioOri) {R0}
set rda_Input(ui_isOrigCenter) {0}
set rda_Input(ui_exc_net) {}
set rda_Input(ui_delay_limit) {1000}
set rda_Input(ui_net_delay) {1000.0ps}
set rda_Input(ui_net_load) {0.5pf}
set rda_Input(ui_in_tran_delay) {120.0ps}
set rda_Input(ui_captbl_file) {}
set rda_Input(ui_cap_scale) {1.0}
set rda_Input(ui_xcap_scale) {1.0}
set rda_Input(ui_res_scale) {1.0}
set rda_Input(ui_shr_scale) {1.0}
set rda_Input(ui_time_unit) {none}
set rda_Input(ui_cap_unit) {}
set rda_Input(ui_sigstormlib) {}
set rda_Input(ui_cdb_file) {}
set rda_Input(ui_echo_file) {}
set rda_Input(ui_qxtech_file) {}
set rda_Input(ui_qxlib_file) {}
set rda_Input(ui_qxconf_file) {}
set rda_Input(ui_pwrnet) {vdd}
set rda_Input(ui_gndnet) {gnd}
set rda_Input(flip_first) {1}
set rda_Input(double_back) {1}
set rda_Input(assign_buffer) {0}
set rda_Input(ui_pg_connections) [list \
{PIN:vdd:} \
{PIN:gnd:} \
]
set rda_Input(PIN:vdd:) {vdd}
set rda_Input(PIN:gnd:) {gnd}

encounter_rc.tcl

###################################
# Run the design through Encounter
###################################

# Setup design and create floorplan
loadConfig ../enc/encounter_rc.conf
#commitConfig

file mkdir ../results/enc

set my_toplevel xxxx

# Create Initial Floorplan
floorplan -r 1.0 0.6 20 20 20 20

# Create Power structures
addRing -spacing_bottom 5 -width_left 5 -width_bottom 5 -width_top 5 -spacing_top 5 -layer_bottom metal5 -width_right 5 -around core -center 1 -layer_top metal5 -spacing_right 5 -spacing_left 5 -layer_right metal6 -layer_left metal6 -nets { gnd vdd }

# Place standard cells
amoebaPlace

# Route power nets
sroute -noBlockPins -noPadRings

# Perform trial route and get initial timing results
trialroute
#buildTimingGraph
#setCteReport
#reportTA -nworst 10 -net > ../results/enctiming.rep.1.placed

# Run in-place optimization
# to fix setup problems
#setIPOMode -mediumEffort -fixDRC -addPortAsNeeded
#initECO ./ipo1.txt
#fixSetupViolation
#endECO

#buildTimingGraph
#setCteReport
#reportTA -nworst 10 -net > ../results/enctiming.rep.2.ipo1

# Run Clock Tree Synthesis
createClockTreeSpec -output ../results/enc/encounter.cts -bufFootprint buf -invFootprint inv
specifyClockTree -clkfile ../results/enc/encounter.cts
ckSynthesis -rguide ../results/enc/cts.rguide -report ../results/enc/report.ctsrpt -macromodel ../results/enc/report.ctsmdl -fix_added_buffers

# Output Results of CTS
trialRoute -highEffort -guide ../results/enc/cts.rguide
extractRC
reportClockTree -postRoute -localSkew -report ../results/enc/skew.post_troute_local.ctsrpt
reportClockTree -postRoute -report ../results/enc/report.post_troute.ctsrpt

# Run Post-CTS Timing analysis
setAnalysisMode -setup -async -skew -autoDetectClockTree
#buildTimingGraph
#setCteReport
#reportTA -nworst 10 -net > ../results/enctiming.rep.3.cts

# Perform post-CTS IPO
#setIPOMode -highEffort -fixDrc -addPortAsNeeded -incrTrialRoute -restruct -topomap
initECO ../results/enc/ipo2.txt
setExtractRCMode -default -assumeMetFill
extractRC
fixSetupViolation -guide ../results/enc/cts.rguide

# Fix all remaining violations
setExtractRCMode -detail -assumeMetFill
extractRC
if {[isDRVClean -maxTran -maxCap -maxFanout] != 1} {
fixDRCViolation -maxTran -maxCap -maxFanout
}

endECO
cleanupECO

# Run Post IPO-2 timing analysis
#buildTimingGraph
#setCteReport
#reportTA -nworst 10 -net > ../results/enctiming.rep.4.ipo2

# Add filler cells
addFiller -cell FILL -prefix FILL -fillBoundary

# Connect all new cells to VDD/GND
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -override

globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -override

# Run global Routing
globalDetailRoute

# Get final timing results
setExtractRCMode -detail -noReduce
extractRC
#buildTimingGraph
#setCteReport
#reportTA -nworst 10 -net > ../results/enctiming.rep.5.final

clearClockDomains
setClockDomains -all
timeDesign -reportOnly -idealClock -pathReports -drvReports -slackReports -numPaths 50 -prefix $my_toplevel -outDir ../results/enc/timingReports

# Output GDSII
streamOut ../results/enc/final.gds2 -mapFile /path>> /osu_freepdk/lib/files/gds2_encounter.map -stripes 1 -units 1000 -mode ALL
streamOut ../results/enc/fdm -mapFile ../results/enc/streamOut.map -libName DesignLib -structureName $my_toplevel -units 2000 -mode ALL
saveNetlist -excludeLeafCell ../results/enc/final.v

# Output DSPF RC Data
rcout -spf ../results/enc/final.dspf

# Run DRC and Connection checks
verifyGeometry
verifyConnectivity -type all

win

puts “**************************************”
puts “* Encounter script finished *”
puts “* Type ‘exit’ to quit *”
puts “* *”
puts “**************************************”

4] Prime Time [pt]

Synopsys PrimeTime is a software tool used for static timing analysis of integrated circuits. A PrimeTime script is a series of commands written in Tcl (Tool Command Language) or in PrimeTime’s proprietary language, PTSL (PrimeTime Scripting Language), that automate the various steps of the static timing analysis process. Here is an example PrimeTime script that performs basic timing analysis on a design:

# Start PrimeTime and read in design and library files
primeTime -file design.v -lib library.lib

# Specify timing constraints
set_input_delay -clock clk -max 1.0
set_output_delay -clock clk -max 1.0
set_clock_uncertainty 0.1

# Analyze timing
report_checks -verbose -path_delay min -path_type full

# Generate timing reports
report_timing -delay_type max -slack_less_than 0.1 -group_endpoints
report_power -toggle

This script first starts PrimeTime and reads in the design file “design.v” and the library file “library.lib”. It then specifies timing constraints for the clock input and output signals, as well as the clock uncertainty. Next, it analyzes the timing of the design and generates a report of timing checks. Finally, it generates timing and power reports based on the specified constraints and settings.

####################
# SETUP #
####################

#1.
set sh_enable_page_mode true

#2.
set search_path {. ./../designs}
set link_path {* ./../libs/tut_lib.db}

#3.
read_verilog ex1_design.v

#4.
link_design

####################
# CONSTRAIN #
####################

#1. check the design’s timing
check_timing

#2. 50% duty cycle, 150Mhz get
create_clock -period 6.666 -name CLK [get_ports clk1]

#3.
set_clock_latency 2.0 CLK

#4.
set_input_delay 2.0 -clock CLK [get_ports in*]
set_output_delay 1.0 -clock CLK [all_outputs]

#5.
report_clock -skew
report_port -input_delay
report_port -output_delay
check_timing

####################
# ENV ATTRIBUTES #
####################

#1.
set_driving_cell -lib_cell IV [all_inputs]

#2.
set_load -pin_load 1 [all_outputs]

#3.
set_wire_load_model -name 10Kgates

#4.
set_operating_conditions -library tut_lib -analysis_type single TYPICAL

####################
# REPORT ON DESIGN #
####################

#1.
report_design

#2.
report_hierarchy

#3.
report_net

#4.
report_cell

#5.
report_reference

#6.
report_clock

####################
# REPORT TIMING #
####################

#1.
report_timing

#2.
report_timing -nets -transition_time -capacitance

#3.
report_timing -nworst 10 -path_type summary

#4.
report_timing -nworst 10 -path_type summary -to [all_outputs]

#5.
report_timing -nworst 10 -path_type summary -from g*/CP -to g*/D

####################
# CLEANUP #
####################

#1.
remove_design -all

#2.
remove_lib -all

5] VCS synopsys

# Set the Verilog source files and libraries

set SRCS {module1.v module2.v}

set LIBS {lib1.v lib2.v}

# Set the VCS compilation flags and defines

set VCS_FLAGS “-sverilog -full64 -debug +define+DEFINE1=1 +define+DEFINE2=0”

# Set the simulation options and defines

set SIM_FLAGS “+access+r +access+rw +define+SIMULATION=1 +define+TESTBENCH=\”tb_top\””

# Compile the Verilog files with VCS

vcs $VCS_FLAGS $SRCS $LIBS

# Run the simulation with VCS

simv $SIM_FLAGS

# Generate the waveform database file

vcd2wlf trace.vcd trace.wlf

# View the waveform using the VCS waveform viewer

dve -vpd trace.wlf

==================================================

chmod +x run_sim.tcl

vcs -full64 –debug < run_sim.tcl

==================================================

This Tcl script file sets the Verilog source files and libraries in the SRCS and LIBS variables, respectively. It then sets the VCS compilation flags and defines in the VCS_FLAGS variable and sets the simulation options and defines in the SIM_FLAGS variable. It then compiles the Verilog files with VCS and runs the simulation with the compiled executable. After the simulation is complete, it generates a waveform database file using vcd2wlf and opens it with the VCS waveform viewer dve.

You can customize this Tcl script file by modifying the SRCS, LIBS, VCS_FLAGS, and SIM_FLAGS variables to match your Verilog project. You can then save it as a Tcl script file with a “.tcl” extension and run it using the terminal:

Make sure to give execute permissions to the Tcl script file before running it:

==================================================

makefile and configuration file

A makefile is a script that automates the build process of a project. It describes how to build, test and package a software application. The makefile is written in a special syntax and executed by the make utility. Here is an example of a makefile for a Verilog project using VCS:

################

# Set the default target
all: sim

# Define the source files and libraries
SRCS = module1.v module2.v
LIBS = lib1.v lib2.v

# Define the simulation executable
sim: $(SRCS) $(LIBS)
vcs -sverilog $(SRCS) $(LIBS)

# Define a cleanup target
clean:
rm -rf simv csrc *.log

##########

This makefile defines three targets:

  • all: This is the default target that builds the simulation executable.
  • sim: This target builds the simulation executable using VCS.
  • clean: This target removes all the simulation files.

To use this makefile, save it as “Makefile” in the root directory of your Verilog project and run the “make” command in the terminal.

A configuration file for VCS is used to customize the simulation settings, such as the compiler flags, simulation options, and waveforms. The VCS configuration file has a “.conf” extension and is passed as an argument to the “vcs” command. Here is an example of a VCS configuration file:

#################

# Set the compilation flags
-v2005 # Use SystemVerilog 2005 syntax
-full64 # Generate 64-bit code
-debug # Enable debug information
+define+DEBUG=1 # Define a macro

# Set the simulation options
+access+r # Allow read access to the simulation hierarchy
+access+rw # Allow read and write access to the simulation hierarchy
+define+SIMULATION=1 # Define a macro

# Set the waveform settings
-wdb trace.wdb # Set the waveform database filename

###############

To use this configuration file, save it as “vcs.conf” in the root directory of your Verilog project and pass it as an argument to the “vcs” command:

vcs -sverilog -f filelist.txt -f vcs.conf
In this example, the “filelist.txt” contains a list of Verilog source files to be compiled and simulated. The “-f” option is used to specify a file containing a list of files to be used as input.

6] NCLAUNCH

# Set the Verilog source files and libraries
set SRCS {module1.v module2.v}
set LIBS {lib1.v lib2.v}

# Set the ncelab compilation flags and defines
set NCELAB_FLAGS “-64bit -access +rwc +define+DEFINE1=1 +define+DEFINE2=0”

# Set the simulation options and defines
set SIM_FLAGS “+access+r +access+rw +define+SIMULATION=1 +define+TESTBENCH=\”tb_top\””

# Compile and elaborate the Verilog files with ncelab
ncelab $NCELAB_FLAGS $SRCS $LIBS

# Create the log file
set LOG_FILE “sim.log”
nclog open -a $LOG_FILE

# Run the simulation with ncsim
ncsim $SIM_FLAGS testbench

# Generate the waveform database file
vcd2wlf trace.vcd trace.wlf

# View the waveform using the nWave waveform viewer
nWave -vpd trace.wlf

# Close the log file
nclog close

This Tcl script file sets the Verilog source files and libraries in the SRCS and LIBS variables, respectively. It then sets the ncelab compilation flags and defines in the NCELAB_FLAGS variable and sets the simulation options and defines in the SIM_FLAGS variable. It then compiles and elaborates the Verilog files with ncelab and creates a log file with nclog. After the simulation is complete, it generates a waveform database file using vcd2wlf and opens it with the nWave waveform viewer. Finally, it closes the log file with nclog.

You can customize this Tcl script file by modifying the SRCS, LIBS, NCELAB_FLAGS, SIM_FLAGS, and LOG_FILE variables to match your Verilog project. You can then save it as a Tcl script file with a “.tcl” extension and run it using the terminal:

nclaunch –input run_sim.tcl

Make sure to give execute permissions to the Tcl script file before running it:

chmod +x run_sim.tcl

 

Please edit the path and top module name, also take care of the files location, this is template edit according to your requirements.

Will update more tcl script here,

Comments are wel-come

 

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