Power line communication HART setup

Hi, after many projects on the power line communication for AC and DC line, There are many power line modems chips are there which convert the bit 1/0 into FSK, like for 1-1200hz, for 0-2200hz which then superimpose on to the power line.

While working with DC power line communication called HART communication for the ds8500 HART chip, I came across it is very tough to make it alone with 4-20ma loop circuit arrangement. Not found well define application circuit around it.

Well most important part is the system setup with the power supply arrangement.

A two node and power supply is shown in the block diagram. As it seen from the diagram there is inductor L is place which will block the any high frequency entering to the power supply of individual node if not place the inside regulator or filtering capacitor will remove any signal on DC line. so logically this L make line float for signal which can be superimpose on or take it to from for receive using coupling capacitor. generally L of value 2mH and 2.2uF capacitor can be used for such setup.

The application diagram of DS8500 from datasheet link

https://www.analog.com/media/en/technical-documentation/tech-articles/introduction-to-the-ds8500-hart-modem.pdf

Modulation waveform

Demodulation waveform

HART slave using DS8500 circuitry and the top-level blocks necessary for an intelligent process transmitter. A temperature process transmitter serves as an example for this circuit. The sensor on the process transmitter measures the system temperature in current or voltage and then passes the data to
the ADC. The ADC, in turn, converts these analog signals to digital equivalents for the microcontroller to process. The microcontroller provides remote memory along with computation power. The microcontroller typically hosts the HART stack and is responsible for the protocol implementation; it also processes the digital data from the HART modem. Microcontroller capabilities can also be used for sensor calibration, linearization and signal  conditioning. The DAC is primarily responsible for driving the current loop. On the master side, the DS8500 can be part of the master modem that resides either on the central control unit or the handheld HART communicator.

shows the master-side configuration. In this case, the DS8500 communicates to the PC through an RS-232 serial port. The HART protocol is usually supported by software that can be installed on the computer.

The more detail circuit found from some where from its evaluation circuit details,

And the DS8500 circuit design as below but it is part of the complete design, here i only given the ds related circuit.

I recommend to use amplifier to boot the fsk out signal from ds8500, which i found in different application note else isolation transform can be used for such amplification with proper turn ratio.

The amplifier in simple form

mosfet is use for the disable the unnecessary signals during ideal time.

Now for AC the, had worded with TDA5051 PLC chip, sharing some information about it, you can go thro its datasheet in details while working on it.

The pin description, DATA in out and TXout and RXin PD pins used for interface with the MC or host controller.

For every  PLC communication AC and DC data sending concept is same, convert the bit 1/0 into its corresponding assigned frequency [FSK] f1/f2 and at the receiver side do the revers to get the bit 1/0. from the block diagram you can see the process data input is placed at DATAin pin which then converted to FSK at the TXout using ROM and dac circuit. Similar at the receiver side analog signal converted in to digital using ADC, filter the signal using digital filter then demodulate it.

There are two application circuit on the bases of isolation [1] non-isolated PLC [2] isolated PLC design.

1] Non isolated PLC circuit is shown below,

1.1] Non-isolated PLC circuit is shown below,

2] Isolated PLC circuit is shown below,

1.functional Description                    

Both transmission and reception stages are controlled either by the master clock of the micro-controller, or by the on-chip reference oscillator connected to a crystal. This holds for the accuracy of the transmission carrier and the exact trimming of the digital filter, thus making the performance totally independent of application disturbances such as component spread, temperature, supply drift and so on. The interface with the power network is made by means of a LC network . The device includes a power output stage able to feed a 120 dBmV (RMS) signal on a typical 30 W load. To reduce power consumption, the IC is disabled by a power-down input (pin PD): in this mode, the on-chip oscillator remains active and the clock continues to be supplied at pin CLKOUT. For low-power operation in reception mode, this pin can be dynamically controlled by the micro controller (see Section “Power-down mode”). When the circuit is connected to an external clock generator , the clock signal must be applied at pin OSC1 (pin 7); OSC2 (pin 8) must be left open. Use of the on-chip clock circuitry is shown. All logic inputs and outputs are compatible with TTL/CMOS levels, providing an easy connection to a standard micro controller I/O port. The digital part of the IC is fully scan-testable.

Two digital inputs, SCANTEST and TEST1, are used for production test: these pins must be left open in functional mode (correct levels are internally defined by pull-up/down resistors).

2 Transmission mode

The carrier frequency is generated by the scanning of a ROM memory under the control of the microcontroller clock or the reference frequency provided by the on-chip oscillator, thus providing strict stability with respect to environmental conditions. High frequency clocking rejects the aliasing components to such an extent that they are filtered by the coupling LC network and do not cause any significant disturbance. The data modulation is applied through pin DATAIN and smoothly applied by specific digital circuitry to the carrier (shaping). Harmonic components are limited in this process, thus avoiding unacceptable disturbance of the transmission channel (according to CISPR16 and EN50065-1 recommendations). A -55 dB total harmonic distortion is reached when using the typical LC coupling network (or an equivalent filter). The D/A converter and the power stage are set in order to provide a maximum signal level of 122 dBmV (RMS) at the output. The output of the power stage (TXOUT) always has to be connected to a decoupling capacitor, because of a DC level of 0.5VDD at this pin, present even when the device is not transmitting. This pin also has to be protected against over voltage and negative transient signals. The DC level of TXOUT can be used to bias an unipolar transient suppressor, as shown in the application diagram. Direct connection to the mains is done through a LC network for low-cost applications. However, a HF signal transformer could be used when power-line insulation has to be performed.

3.Receiving mode:

The input signal received by the modem is applied to a wide range input amplifier with Automatic Gain Control (AGC) (-6 to +30 dB). This is basically for noise performance improvement and signal level adjustment that ensures a maximum sensitivity of the A/D converter. Then an 8-bit A/D conversion is performed, followed by digital bandpass filtering, in order to meet the CISPR normalization and to comply with some additional limitations encountered in current applications. After digital demodulation, the base band data signal is made available after pulse shaping. The signal pin (RXIN) is a high-impedance input, which has to be protected and DC decoupled for the same reasons as with pin TXOUT. The high sensitivity (82 dBmV) of this input requires an efficient 50 Hz rejection filter (realized by the LC coupling network) also used as an anti-aliasing filter for the internal digital processing The output of the power stage (TXOUT) always has to be connected to a decoupling capacitor, because of a DC level of 0.5VDD at this pin, present even when the device is not transmitting. This pin also has to be protected against over voltage and negative transient signals. The DC level of TXOUT can be used to bias an unipolar transient suppressor, as shown in the application diagram. Direct connection to the mains is done through a LC network for low-cost applications. However, a HF signal transformer could be used when power-line insulation has to be performed.

Comments are welcome.